The present invention relates to multi-core processor architecture, and more specifically, to systems and methods for dynamically detecting and identifying failing cores in a multi-core processor test environment.
A multi-core processor is a processing system composed of two or more functionally independent cores. The cores are typically integrated onto a single integrated circuit die or they may be integrated onto multiple dies in a single chip package. A many-core processor is one in which the number of cores is large enough that traditional multi-processor test and performance evaluation techniques are no longer efficient. This threshold is somewhere in the range of several tens of cores and can require self-diagnostics to determine if any of the cores are failing. Multi-core architecture with built-in self-test (BIST) has become a design trend for VLSI chips due to their needs of high performance and high reliability. Efficient approaches for diagnosing fail cores are thus desirable for yield enhancement.
A problem encountered while concurrently testing multiple cores in a BIST test design environment is to dynamically detect and identify the failing core in real-time and exclude that core from further testing or terminate testing for insufficient number of functional cores. Additionally, an associated problem is to identify the failing test cycle for further diagnostics. It is also desirable to determine dynamic error or detect failures in high reliability communication and data transfer sub-systems. In addition, there persists a generic problem in logic systems to dynamically determine the dominant state of multiple signal bits or data channels. The dominant state is the determination of the majority of the logic state, either “0” or “1”, for n-bits at a specific point in time.